High powered very large scale integration (VLSI) circuits are widely used in the electronics industry. Major uses include clock buffers, wordline drivers and I/O buffers. During their operation, VLSI circuits generate heat internally. This self-heating increases the junction temperature in the device, and can result in failure of the VLSI circuit.
Generally, VLSIs are comprised of a plurality of field effect transistors (FETs) laid out on a substrate. FIG. 1 is a simplified diagram of an FET showing the self-heating. Shown in FIG. 1 are channel 101, gate 102, oxide 103 and substrate 104. Within the channel 101 to gate 102 junction, the self-heating is shown as bursts 105. Points where the source voltage Vs, the drain voltage Vd, and the gate voltage Vg are also shown. As the voltages are applied to the source, gate and drain of the device, internal heating begins to occur. As shown in this simplified diagram, the self-heating bursts 105 are non-uniform and in their distribution and degree.
FIG. 2 is a schematic diagram illustrating a single finger VLSI circuit. Shown in FIG. 2 is a single finger VLSI 201. P junction FET (PFET) 202 and N junction FET (NFET) 203 comprise the VLSI 201 shown in FIG. 2. PFET 202 is comprised of a source 202a, a drain 202b, and a gate 202c, and NFET 203 is comprised of a source 203a, a drain 203b, and a gate 203c. Voltage (+V) 205 and Ground (GND) 206 are also depicted in FIG. 2. PFET 202 and NFET 203 are controlled through gate connector 204. The gates and gate connector are shown in a hatched detail. The gate connector 204 extends horizontally between gates 202c and 203c. The “single finger” structure of the VLSI 201 refers to the single vertical part of the gate 204. As voltages are applied to the VLSI 201, the regions about the PFET 202 and the NFET 203 will begin to generate heat due to the flow of current through each of the PFET 202 and NFET 203. As stated earlier, this heat, if allowed to reach critical values, can deteriorate ideal operation or completely destroy the VLSI 201.
Polysilicon, or polycrystalline silicon, has long been used as the conducting gate and gate connector material in MOSFET and CMOS processing technologies. For these technologies it is deposited using reactors at high temperatures. More recently, polysilicon is being used in very large scale integration (VLSI) electronics. The main advantage of polysilicon is that it allows more complex, high-speed circuitry to be created on the glass substrate.
FIG. 3 is a schematic diagram illustrating a multi-finger VLSI circuit. Shown in FIG. 3 is a multi-finger VLSI 301. A plurality of P junction FETs (PFETs) 302 and a plurality of N junction FETs (NFETs) 303 comprise the VLSI 301 shown in FIG. 3. Each PFET 302 is comprised of a source 302a, a drain 302b, and a gate 302c, and each NFET 303 is comprised of a source 303a, a drain 303b, and a gate 303c. Voltage (+V) 305 and Ground (GND) 306 are also depicted in FIG. 3. Each PFET 302 and each NFET 303 are controlled through gate connector 304. The gates and gate connectors are shown in a hatched detail. The gate connector 304 extends horizontally between each of the FETs. Vout 307 is the output voltage points for the FETs. The “multi-finger” structure of the VLSI 301 refers to the plurality of 302c gates and plurality of 303c gates. As voltages are applied to the VLSI 301, the regions about the PFETs 302 and the NFET 303 will begin to generate heat due to the flow of current through each of the PFETs 302 and NFETs 303. As stated earlier, this heat, if allowed to reach critical values, can deteriorate ideal operation or completely destroy the VLSI 301.
Currently, various models are utilized to estimate this internally generated heat. One such model is the Berkeley Short-channel IGFET Model for MOS transistors (BSIM). The BSIM and other design models approximate the internal operations of a circuit at a design stage. These models use know values and operating parameters of the circuit components to assist in the design of the final integrated circuit using highly mathematical statistical models. The BSIM in particular also includes statistical models to estimate the internal heating of the integrated circuit. Although the BSIM is a good method to approximate the internal temperature of the integrated circuit, using approximations and statistical models can only produce estimated results.
During the operational states of the circuits, the self-heating is also know to be non-uniform throughout the topology of the circuit. Again, only approximations and estimations are available to measure the differences in temperature occurring at these differing levels of the integrated circuit. As a result, the integrated circuits that are designed using the conventional methods cannot accurately account for the variations in temperature throughout the cross sections of the final integrated circuit product.